Method for storing data in a memory device with the possibility of access to redundant memory cells

ABSTRACT

The invention provides a method for storing data in a memory device having memory cells arranged in memory cell rows and memory cell columns, in which system defects brought about by defective memory cells are eliminated, in which case redundant memory cells are provided in the memory device; a predeterminable access mode for accessing the redundant memory cells is provided; and defective memory cells of the memory device are replaced by the redundant memory cells in a manner dependent on the predetermined access mode during operation of the memory device.

[0001] The present invention relates to a method for storing data and adevice for storing data, and relates in particular to a method forstoring data in a memory device having memory cells arranged in memorycell rows and memory cell columns, system defects brought about bydefective memory cells being eliminated.

[0002] During the conception, the design and the construction of memorymodules it is unavoidable that system failures brought about bydefective memory cells will occur during the operating time of a memorymodule, i.e. while the memory module is in an active state in a circuit.

[0003] In this case, the exact construction of a memory module isinsignificant, so that memory modules are hereinafter referred to quitegenerally as “memory devices”. Due to the increasing complexity ofelectronic circuits and the continuously increasing integration densityof circuit units (“chips”), system failures of this type result forexample from problems in the reliability of the memory module, broughtabout by electromigration, etc.

[0004] Many electronic systems in which memory units are arranged reactvery sensitively to an occurrence of memory cell defects, so that therequirements made of reliability and availability of memory units alsoincrease as integration density increases. Due to the increasingcomplexity of electronic circuit units, it is necessary to effect atrade off between an efficiency of a circuit design and a conception ofthe hardware to be created. Existing hardware concepts require that theycan be used in different circuit environments, even when defectivememory cells occur.

[0005]FIG. 2 shows a timing diagram of a conventional sequence when amemory cell defect occurs in a conventional memory device. In FIG. 2, areference symbol 201 designates a conventional system availability,which can vary between 0% and 100%.

[0006] A time axis 202 (“Time”) designates different points in time andis arranged on a scale such that it is possible to represent a timeprogression from an occurrence of a memory cell defect 203 up to the endof a booting operation 207. Conventionally, the entire system has to beswitched off when a memory cell defect 203 occurs, so that a beginning204 of a system failure results directly after an occurrence of a memorycell defect 203.

[0007] The consequence of conventional system failures is that a systemavailability 201 falls from 100% (assuming that no further defectsoccurred) to 0%. Finally, the defective hardware is exchanged, which isexpensive and time-consuming particularly in the case of complexelectronic systems. A reference symbol 206 specifies a so-called memoryexchange time duration.

[0008] After the memory exchange time duration 206 has elapsed, thetotal system failure ends, i.e. the conventional system availability 201rises again slowly, proceeding from 0%. After a booting time duration208, the full (100%) conventional system availability 201 is reachedagain at the end 207 of the booting operation.

[0009] Consequently, one disadvantage of conventional methods foreliminating a memory defect is that a long system failure time occurs,which, with reference to FIG. 2, occurs as a sum of the memory exchangetime duration 206 and the booting time duration 208.

[0010] A further disadvantage of conventional methods for recovering asystem availability 201 is that exchanging defective hardware orswitching off the entire system is expensive and impracticable, undercertain circumstances, since total system failures are to be avoided.

[0011] Consequently, it is an object of the present invention to providea method for storing data in a memory device in which defective memorycells of a memory unit are replaced by redundant memory cells during theoperating time of a memory.

[0012] The redundant memory cells are expediently accessed in such a waythat a system restart or system booting is avoided.

[0013] This object is achieved according to the invention by means ofthe method specified in patent claim 1 and by means of a memory devicehaving the features of patent claim 9.

[0014] Further refinements of the invention emerge from the subclaims.

[0015] An essential concept of the invention consists in a systemavailability being completely or at least partly maintained when adefect occurs in memory cells, in that redundant memory cells present inthe memory device undertake the function of defective memory cells.

[0016] Thus, one advantage of the present invention is that a systemavailability (this is possibly slightly reduced) can be maintained evenwhen defects occur in memory cells.

[0017] Moreover, it is expedient that the method according to theinvention advantageously utilizes effectively always existing redundantmemory cells, thereby enabling economical circuit development.

[0018] In particular, in the case of a system failure caused bydefective memory cells, it is not necessary to exchange systemcomponents. In this way, no additional hardware costs arise and acost-efficient procedure in the case of memory cell defects is achieved.

[0019] Furthermore, one advantage of the method according to theinvention is that the time of reduced system availability is reduced, sothat replacement of defective memory cells can be performed in a shorttime during operation of the memory unit.

[0020] The invention's method for storing data in a memory device havingmemory cells arranged in memory cell rows and memory cell columns,system defects brought about by defective memory cells being eliminated,essentially has the following steps:

[0021] a) provision of redundant memory cells present in the memorydevice;

[0022] b) provision of a predeterminable access mode for accessing theredundant memory cells; and

[0023] c) replacement of defective memory cells of the memory device bythe redundant memory cells in a manner dependent on the predeterminedaccess mode during operation of the memory device.

[0024] Advantageous developments and improvements of the respectivesubject matter of the invention can be found in the subclaims.

[0025] In accordance with one preferred development of the presentinvention, replacement of the defective memory cells of the memorydevice by the redundant memory cells is provided in a reversiblefashion. It is expediently possible for already allocated redundantmemory cells which have replaced defective memory cells to be providedwith other defective memory cells of the memory device.

[0026] In accordance with yet another preferred development of thepresent invention, a predeterminable number of redundant memory cellrows or a predeterminable number of redundant memory cell columns areprovided.

[0027] It is thus possible, in an advantageous manner, that, if adefective memory cell occurs in the memory device, the system candetermine whether a corresponding memory cell row or a correspondingmemory cell column is used for the replacement of the defective memorycell or the defective memory cells.

[0028] In a further expedient manner, replacement may be provided byprogramming a register which, by way of example, comprises both anactivation bit and the defective column or row address.

[0029] In accordance with yet another preferred development of thepresent invention, defective memory cells of the memory device arereplaced by an exchange of at least one memory cell row and/or at leastone memory cell column in a manner dependent on the predetermined accessmode during operation of the memory device.

[0030] In accordance with yet another preferred development of thepresent invention, an exchange of defective memory cells of the memorydevice is carried out in a manner dependent on the predetermined accessmode during operation of the memory device by programming an accessregister, an activation bit and at least one address of the memory cellrow and/or the memory cell column which are/is to be replacedadvantageously being provided.

[0031] In accordance with yet another preferred development of thepresent invention, the predeterminable access mode for accessing theredundant memory cells during operation of the memory device is providedby a test mode of the memory device.

[0032] In accordance with yet another preferred development of thepresent invention, redundant memory cells for storing an additionalinformation item describing a defect correction are provided.

[0033] Consequently, it is advantageously possible to record for exampleinformation about the occurrence of a defect in memory cells.

[0034] The memory device according to the invention furthermore has:

[0035] a) memory cells arranged in memory cell rows and memory cellcolumns and serving for storing data; and

[0036] b) redundant memory cells for replacing defective memory cellsduring the operation of the memory device.

[0037] Exemplary embodiments of the invention are illustrated in thedrawings and are explained in more detail in the description below.

[0038] In the drawings:

[0039]FIG. 1 shows a timing chart for the replacement of defectivememory cells in a memory device by redundant memory cells of the memorydevice during operation of the memory device; and

[0040]FIG. 2 shows a timing chart of a conventional method for replacingdefective memory cells.

[0041] In the figures, identical reference symbols designate identicalor functionally identical components or steps.

[0042] The timing chart shown in FIG. 1 reveals that a systemavailability 101 has not completely fallen to 0 (0%) during the entireoperating time or during the entire operation of the memory device orsystem in which the memory device is integrated. A profile of the systemavailability 103 is plotted against a time axis 103 (“Time”), it beingassumed that a memory cell defect occurs during the operating time ofthe memory device.

[0043] First let it be assumed that a 100% system availability 101 isinitially present. When a memory cell defect occurs, designated by thereference symbol 1 in FIG. 1, the system availability will decreased.Let it be assumed that a memory cell defect has occurred such that thesystem availability is reduced to a reduced value, i.e. the reducedsystem availability 102 (dashed line in FIG. 1).

[0044] Further operation of the memory device is advantageously ensured,although with (possibly only slight) reduced system availability 101.After a memory cell defect has occurred (step 1), defect localizationand redundancy selection are carried out in step 2 (FIG. 1).

[0045] When a defective memory cell occurs, the system determineswhether a corresponding memory cell row or a corresponding memory cellcolumn is replaced. The replacement is effected for example byprogramming a register which has both an activation bit and an addressof a defective column and/or row. In this case, an access register wouldbe necessary per redundant memory cell row or memory cell column. Alocalization of a defective memory cell and an access to or a selectionof redundant memory cells are likewise effected in FIG. 2.

[0046] Once defect localization and redundancy selection has beencarried out in step 2, the system provides a bypass for accessingredundant memory cells in an access register. The access registerprovides the bypass in a step 3, which directly follows step 2 andprevents a further reduction of the system availability 101.Consequently, a defect localization, a redundancy selection and a bypassfor accessing redundant memory cells can be provided during theoperating time of the memory device.

[0047] After step 3, the system advances, since defective memory cellshave been replaced by redundant memory cells, to step 4, in which thefull (100%) system availability 101 has been recovered.

[0048] Furthermore, the system can determine, in the memory device,redundant memory cells which are provided for storing an additionalinformation item describing a defect correction. Identification of thesememory cells which store an additional information item describing adefect correction serves for rapidly finding a memory cell defect andfacilitating a determination of a defect progression in a memory device.

[0049] With regard to the time sequence of a conventional method forreplacing defective memory cells in a memory device as illustrated inFIG. 2, reference is made to the introduction to the description.

[0050] Although the present invention has been described above usingpreferred exemplary embodiments, it is not restricted thereto, butrather can be modified in diverse ways.

[0051] Moreover, the invention is not restricted to the applicationpossibilities mentioned.

LIST OF REFERENCE SYMBOLS

[0052] In the figures, identical reference symbols designate identicalor functionally identical components or steps.

[0053]1 Occurrence of a memory cell defect

[0054]2 Defect localization and redundancy selection bypass

[0055]3 Accessing redundant memory cells

[0056]4 Re-establishment of full system availability

[0057]101 System availability

[0058]102 Reduced system availability

[0059]103 Time axis

[0060]201 Conventional system availability

[0061]202 Time axis

[0062]203 Occurrence of a memory cell defect

[0063]204 Beginning of system failure

[0064]205 End of system failure

[0065]206 Memory exchange time duration

[0066]207 End of booting operation

[0067]208 Booting time duration

1. Method for storing data in a memory device having memory cells arranged in memory cell rows and memory cell columns, in which system defects brought about by defective memory cells are eliminated, characterized in that a) redundant memory cells are provided in the memory device; b) a predeterminable access mode for accessing the redundant memory cells is provided; and c) defective memory cells of the memory device are replaced by the redundant memory cells in a manner dependent on the predetermined access mode during operation of the memory device.
 2. Method according to claim 1, characterized in that replacement of the defective memory cells of the memory device by the redundant memory cells is provided in a reversible fashion.
 3. Method according to one or both of claims 1 and 2, characterized in that a predeterminable number of redundant memory cell rows are provided.
 4. Method according to one or more of the preceding claims, characterized in that a predeterminable number of redundant memory cell columns are provided.
 5. Method according to claims 3 and 4, characterized in that defective memory cells of the memory device are replaced by an exchange of at least one memory cell row and/or at least one memory cell column in a manner dependent on the predetermined access mode during operation of the memory device.
 6. Method according to claims 1 and 3 to 5, characterized in that an exchange of defective memory cells of the memory device is carried out in a manner dependent on the predetermined access mode during operation of the memory device by programming an access register which contains an activation bit and at least one address of the memory cell row and/or of the memory cell column which is to be replaced.
 7. Method according to claims 1 and 3 to 5, characterized in that the predeterminable access mode for accessing the redundant memory cells during operation of the memory device is provided by a test mode of the memory device.
 8. Method according to claim 1, characterized in that redundant memory cells for storing an additional information item describing a defect correction are provided.
 9. Method device having: a) memory cells arranged in memory cell rows and memory cell columns and serving for storing data; and b) redundant memory cells for replacing defective memory cells during the operation of the memory device.
 10. Memory device according to claim 9 characterized in that redundant memory cells for storing an additional information item describing a defect correction are provided. 